In some cases, a variable frequency divider capable of making a frequency dividing ratio variable is used as a part of a phase locked loop (PLL), for example.
That is, a variable frequency divider may be used to frequency-divide an output signal of a voltage controlled oscillator (VCO) in the PLL with a set frequency dividing ratio.
As a configuration of a variable frequency divider, a configuration in which a plurality of dual modulus frequency dividers is connected in series is known.
Further, as the dual modulus frequency divider, for example, a frequency divider which performs an operation as described below is known.
When the dual modulus frequency divider receives a mod signal which is a control signal from the dual modulus frequency divider on a subsequent stage, in a case in which the mod signal indicates that the frequency dividing ratio is to be fixed, the dual modulus frequency divider frequency-divides a clock signal output from the dual modulus frequency divider on a preceding stage by 2 and outputs the frequency divided signal of the clock signal to the dual modulus frequency divider on the subsequent stage.
In a case in which the mod signal indicates that the frequency dividing ratio is allowed to be variable, the dual modulus frequency divider performs the following operation. When the externally provided frequency dividing ratio setting data is a signal of L level, the dual modulus frequency divider frequency-divides the clock signal output from the dual modulus frequency divider on the preceding stage by 2 and outputs the frequency divided signal of the clock signal to the dual modulus frequency divider on the subsequent stage. When the frequency dividing ratio setting data is a signal of H level, the dual modulus frequency divider frequency-divides the clock signal output from the dual modulus frequency divider on the preceding stage by 3 and outputs the frequency divided signal of the clock signal to the dual modulus frequency divider on the subsequent stage.
Note that, a dual modulus frequency divider outputs a mod signal output from the dual modulus frequency divider on the subsequent stage to the dual modulus frequency divider on the preceding stage.
In a case of the variable frequency divider in which n dual modulus frequency dividers each of which has the configuration as described above are connected in series, by updating the frequency dividing ratio setting data provided to the n dual modulus frequency dividers, it is possible to operate the variable frequency divider with a frequency dividing ratio within a range of 2n to 2n+1−1.
Further, in a variable frequency divider in which the n dual modulus frequency dividers are connected in series, it is assumed that the first stage to the m-th stage dual modulus frequency dividers form a former dual modulus frequency divider, and the (m+1)-th stage to the n-th stage, being the last stage, dual modulus frequency dividers form a latter dual modulus frequency divider. In such a variable frequency divider, it is possible to invalidate last some dual modulus frequency dividers included in the latter dual modulus frequency divider.
In a case in which the last some dual modulus frequency dividers are invalidated, the last some dual modulus frequency dividers do not contribute to the frequency dividing operation of the variable frequency divider. Consequently, the number of dual modulus frequency dividers contributing to the frequency dividing operation of the variable frequency divider decreases. As a result, it becomes possible to support a smaller frequency dividing ratio than that in a case in which all the dual modulus frequency dividers contribute to the frequency dividing operation.
For example, in the PLL, it is sometimes necessary to realize the frequency dividing ratio of a decimal number. In such a case, since the ΔΣ modulation is applied to the frequency dividing ratio, the variable frequency divider should operate following a dynamically changing frequency dividing ratio pattern.
In the variable frequency divider disclosed in following Patent Literature 1, in order to make it possible to operate following the dynamically changing frequency dividing ratio pattern, the internal states of invalidated dual modulus frequency dividers are initialized such that the operation when the invalidated dual modulus frequency dividers are validated next time is constant.